1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to an assembly and method for constructing chip assemblies having fine pitch interconnections.
2. Description of the Related Art
Currently, electronic devices require faster and more compact systems that pack a greater number of components into a smaller chip substrate area. The increased number of components on the chip increases the number of interconnections in the finite spaced offered by the chip. Interconnections are usually conducted via bonding pads or solder bumps through a flip-chip technique. Reducing the distance between the bonding pads, or the xe2x80x9cpitchxe2x80x9d increases the number of interconnects available on the chip, thereby increasing packaging density and reducing packaging weight. Fine pitch assemblies often rely on the ability to etch or deposit very fine traces onto a carrier material to create the interconnects.
FIGS. 1 and 2 illustrate conventionally-known flip-chip technology used to physically and electrically connect two microchips together. FIG. 1 shows two chips 100 and 102 that are bonded together via solder bumps or bonding pads 104 and 106, respectively. As can be seen in the Figure, the solder bumps 104, 106 are aligned together so that corresponding solder bumps 104, 106 on each chip 100, 102 touch only each other and not any other solder bumps 104, 106. If the solder bumps 104, 106 are spaced a relatively large distance apart, that is, if the pitch P allows sufficient spacing in between the solder bumps, alignment is relatively simple even if an automated process is used. The pitch P of the solder bumps 104, 106 using this method cannot be reduced to less than 25 microns, making the structure and method shown in FIGS. 1 and 2 unsuitable for applications require very fine pitch structures.
More particularly, if the pitch is reduced beyond the alignment capabilities of the bonding pad structure, the likelihood of misalignment increases as can be seen in FIG. 2. Misalignment can often occur simply because of the difficulty that automated systems have in aligning the solder bumps with the required precision, often causing a given solder bump or bonding pad to touch two other solder bumps or pads to form a undesirable bridge connection. Attempts to increase the precision of alignment between the solder bumps may slow the manufacturing process to such a degree that the overall yield is too low for cost-effective manufacturing.
There is a need for a fine pitch flip chip assembly process that allows cost-effective manufacturing of flip-chip assemblies without encountering the alignment problems present in known processes.
Accordingly, the present invention is directed to a flip chip method and assembly that is suitable for fine pitch devices. The invention includes applying a conductive layer on a substrate and then forming an interconnect pattern on the conductive layer of the substrate after the conductive portions of a die have been attached to the conductive layer on the substrate. In one embodiment, the die is attached to a substrate having a base layer that supports the conductive layer. A portion of the base layer is cut away to expose the conductive layer, and then the interconnect pattern is etched into the conductive layer via a laser. A sealing layer may be deposited over the exposed conductive layer after etching to protect the interconnect pattern and/or act as a heat sink for the assembly.
Because the interconnect pattern is formed only after the die has been attached to the substrate, the alignment between the conductive portions of the die and the pattern is automatically conducted during the pattern formation process. As a result, there is no need to precisely align the die with any portion of the substrate as the die and substrate are connected together, making the production of fine pitch devices more cost-effective without sacrificing accurate alignment between the conductive portions of the die and the interconnect pattern on the substrate.